Various communications protocols that support high-speed links use a PLL as a frequency synthesizer and also as a noise filter. For example, the PCI Express (PCIE) standard defines specifications for PLLs implemented in transmitter and receiver bus agents for such communications. The PCIE standard is an extension of the PCI standard that uses existing PCI programming concepts. A typical PLL includes a phase-frequency detector and a closed loop feedback divider. The feedback divider has a particular set of divider values based on a desired PLL output clock signal frequency. The phase-frequency detector compares the phase of a reference clock input signal to an internal PLL feedback clock signal. The phase-frequency detector also outputs a signal to adjust the frequency of the PLL clock output in a direction that eliminates a phase difference between the reference clock signal and the feedback clock signal. When the phases and frequencies of the reference clock signal and the PLL clock output signal are aligned, the PLL output signal is “locked” to the reference clock signal.
As communication standards such as the PCIE standard continue to specify increasing data rates, the specifications of the associated transmitter and receiver PLLs become increasingly difficult to meet. For example, historically the PCIE standard has doubled the PCIE bandwidth for each major revision (generally every 3-4 years).
Certain known PLL implementations include adjustment circuits to tune parameters of the PLL. However, when process, voltage, and temperature variations are taken into account, generally the adjustment circuits have difficulty meeting the stricter PLL specifications. As an example of one such specification, many communication standards continue to tighten the amount of jitter that is allowed to propagate from the reference clock signal to the PLL output clock signal. In particular, the PCIE standard defines PLL bandwidth ranges and peaking values for both the transmitter and receiver, placing an upper limit on the amount of reference clock jitter that the transmitter propagates to the receiver over the high speed link. When both the transmitter and receiver PLLs operate within “right sized” bandwidth and peaking values, the receiver is able to perform proper clock and data recovery, and maintain compatibility with the remote transmitter on the other side of the link.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.